83C694D datasheet(7/33 Pages) SMSC

7 / 33 page

2.0

ARCHITECTURE

The 83C694D can be used as an AUI device or as

a twisted-pair interface device.

When used in combination TPI/AUI applications,

the 83C694D is part of a three-device set that

implements the complete IEEE 802.3-compatible

network node electronics (see Figure 1-1).

The 83C690 Ethernet LAN Controller (ELC) and the

83B692 Ethernet Transceiver (ET) comprise the

other two devices in the set. The 83C690 provides

media access protocol functions and performs buff-

er management tasks, while the 83B692 serves as

a coaxial cable line driver/receiver and collision

detector.

The 83C694D Twisted-Pair Interface provides the

interface between the 83C690 ELC and the 83B692

ET. When transmitting, the device converts non-re-

turn-to-zero (NRZ) data from the controller into

Manchester encoded data, then sends this data to

the transceiver.

When receiving, the device reverses the process

using an analog phase-locked loop that decodes 10

Mbit/sec signals with up to

±20 nsec of jitter.

When the 83C694D is used as a twisted-pair (TP)

interface, its on-chip transmitter and receiver (sepa-

rate from the AUI inputs and outputs) connect to the

network through a transformer and filter. In this

application, the 83C694D is used with the 83C690

providing controller and protocol functions, and the

83B692 is not used.

The 83C694D Twisted-Pair Interface is comprised

of these functional blocks:

•

Oscillator

•

Manchester Encoder and Differential Driver

•

Manchester Decoder

•

Collision Translator

•

Loopback Capabilities

•

TP Differential Driver

•

TP Differential Receiver

•

Link Test Function

•

AUI / TP Autoselect

•

Jabber & SQE Test Functions

•

Status Indications

The rest of this section describes each of these

circuits in more detail, including suggestions, where

appropriate, for designing external circuits consis-

tent with the 802.3 standard.

2.1

OSCILLATOR

Control is provided either by a 20 MHz, parallel

resonant crystal connected between X1 and X2, or

by an external clock connected at X1. The oscilla-

tor’s 20 MHz output is divided in half to generate

the 10 MHz transmit clock for the Ethernet LAN

controller and to provide the internal clock signals

for the encoding and decoding circuits.

Figure 2-1 provides a diagram of this connection.

20 MHz

CL - CP

CL = Load capacitance specified by crystal manufacturer

CP = Total parasitic capacitance including:

a) 83C694C input capacitance between X1 and X2

(typically 5 pF)

b) PC board traces, plated through holes, socket capacitances

FIGURE 2-1. CRYSTAL CONNECTION

DIAGRAM

83C694D

ARCHITECTURE

83C694D Datasheet(PDF) 7 Page - SMSC Corporation

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