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ADS5510

SLAS499 – JANUARY 2007

In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive

overdrive, the output code is 0x7FF in straight offset binary output format and 0x3FF in two's complement output

format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x400

in two's complement output format. These outputs to an overdrive signal are ensured through design and

characterization.

The output circuitry of the ADS5510, by design, minimizes the noise produced by the data switching transients,

and, in particular, its coupling to the ADC analog circuitry. Output D1 (pin 51) senses the load capacitance and

adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in

the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have

nearly the same load as D1 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply

voltage or temperature. Placing external resistors in series with the outputs is not recommended.

The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum

sampling frequency. Table 5 and Table 6 show the setup, hold, input clock to output data delays, and rise and

fall times for different sampling frequencies with the DLL on and off, respectively.

Table 7 and Table 8 show the rise and fall times at additional sampling frequencies with DLL on and off,

respectively.

Desired setup time = t

Desired hold time = t

Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

105

2.4

3.1

2.2

2.6

1.7

2.6

5.8

7.3

4.4

5.1

3.3

3.8

93

3.2

4.6

2.3

3.7

80

2.8

3.7

2.8

3.3

0.5

1.7

5.3

7.9

5.8

6.6

4.4

5.3

65

3.8

4.6

3.6

4.1

–0.5

0.8

5.3

8.5

6.7

7.2

5.5

6.4

Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

80

3.2

4.2

1.8

3

3.8

5

8.4

11

5.8

6.6

4.4

5.3

65

4.3

5.7

2

3

2.8

4.5

8.3

11.8

6.6

7.2

5.5

6.4

40

8.5

11

2.6

3.5

–1

1.5

8.9

14.5

7.5

8

7.3

7.8

20

17

25.7

2.5

4.7

–9.8

2

9.5

21.6

7.5

8

7.6

8

10

27

51

4

6.5

-30

-3

11.5

31

2

284

370

8

19

185

320

515

576

50

82

75

150

Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)

CLKOUT Jitter,

CLKOUT, Rise Time

CLKOUT, Fall Time

Input-to-Output Clock Delay

Peak-to-Peak

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

105

2

2.2

1.7

1.8

175

250

4

4.7

5.5

80

2.5

2.8

2.1

2.3

210

315

3.7

4.3

5.1

65

3.1

3.5

2.6

2.9

260

380

3.5

4.1

4.8

24

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