PCD3359AP datasheet(19/32 Pages) PHILIPS

19 / 32 page

1998 May 11

Philips Semiconductors

Product speciﬁcation

8-bit microcontroller with DTMF

generator and 128 bytes EEPROM

PCD3359A

TIMING

Although the PCD3359A operates over a clock frequency

range from 1 to 16 MHz, fxtal = 3.58 MHz will usually be

chosen to take full advantage of the frequency generator

section.

10 RESET

In addition to the conditions given in the

“PCD33XXA

Family” data sheet, all derivative registers are cleared in

the reset state.

11 IDLE MODE

In Idle mode, the frequency generator, the EEPROM and

the Timer 2 sections remain operative. Therefore, the

IDLE instruction may be executed while an erase and/or

write access to EEPROM is in progress.

12 STOP MODE

Since the oscillator is switched off, the frequency

generator, the EEPROM and the Timer 2 sections receive

no clock. It is suggested to clear both the HGF and the

LGF registers before entering Stop mode. This will cut off

the biasing of the internal amplifiers, considerably

reducing current requirements.

The Stop mode must not be entered while an erase

and/or write access to EEPROM is in progress. The STOP

instruction may only be executed when EWP in EPCR is

zero. The Timer 2 section is frozen during Stop mode.

After exit from Stop mode by a HIGH level on CE/T0,

Timer 2 proceeds from the held state.

The Port 0 Wake-up interrupt function remains operative

during Stop mode (depending only on the EPIn bits in

“PCD33xxA family” data sheet, Stop mode may be left by

a Port 0 Wake-up interrupt event (see Section 8.2).

13 INSTRUCTION SET RESTRICTIONS

Please note the following:

• ROM space being restricted to 2 kbytes, the

‘SEL MB1/2/3’ instructions would define non-existing

program memory banks and should therefore be

avoided

• RAM space being restricted to 64 bytes, care should be

taken to avoid accesses to non-existing RAM locations.

14 OVERVIEW OF PORT AND POWER-ON-RESET

CONFIGURATION

All standard quasi-bidirectional I/O ports are available; see

“PCD33xxA family” data sheet.

• Port 0: 8 parallel port lines P0.0 to P0.7 or wake-up

interrupts

• Port 1: 8 parallel port lines P1.0 to P1.7

• Port 2: 4 parallel port lines P2.0 to P2.3.

Table 25 Port and Power-on-reset configuration

See notes 1 and 2.

Notes

1. Port output drive: 1 = standard I/O; 2 = open-drain I/O, see

“PCD33xxA family” data sheet.

2. Port state after reset: S = Set (HIGH) and R = Reset (LOW).

3. The melody output drive type is push-pull.

COVERED

BY OTP

PORT 0

PORT 1

PORT 2

VPOR

01234567012345

0123

PCD3756A

1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R

1R(3)

1.3 V

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