PCD3745A datasheet(14/32 Pages) PHILIPS

14 / 32 page

1999 Feb 02

Philips Semiconductors

Product speciﬁcation

8-bit microcontroller with 4.5 kbytes OTP

memory and 32 kHz real-time clock

PCD3745A

PERIPHERAL COUNTER 1 AND COUNTER 2

The PCD3745A has two on-chip 16-bit peripheral

counters: Counter 1 and Counter 2. Both counters can

count pulses in the frequency range of 0 to 1 MHz and

both will operate in all modes of the microcontroller (Idle,

Stop and Operating modes).

The count process and the interrupt on overflow function

for each counter is enabled/disabled by setting the

appropriate ECx and ECxI bits in the Peripheral Counter

Control Register (PCCR). The count process starts with

setting the ECx bit to a logic 1 and can be stopped in every

state by resetting the ECx bit to a logic 0. The counter

inputs are CLK1 for Counter 1 and CLK2 for Counter 2.

Each counter input is connected to a Schmitt trigger in

order to reduce noise susceptibility. A falling edge of the

pulses on these inputs will increment the enabled counters

by one. The 16-bit counters are also byte-wise read and

writeable, e.g. they can be set to a specific value, for

example to count less than 216 events (refer to Table 13 for

The 16-bit counters and the PCCR (see Table 8) are set to

0000H and 00H respectively, after reset.

Counting events during a write access may be lost. During

a read access they are considered when the length of the

count pulse is greater than 2/fxtal + 500 ns. To ensure

correct operation it is recommended to disable the count

process during a read or write operation to the counter

registers.

In the count mode, if the ECxI bit is set, an overflow (count

transition from FFFFH to 0000H) of the counter will set the

CxF bit, which starts the interrupt sequence. CxF is wired

ORed with CE/T0 and consequently the effect is the same

as an external interrupt. Within this interrupt sequence the

interrupt source must be searched and CxF should be

reset to enable the microcontroller to service future

interrupts. CxF is set by hardware or software but can be

reset by software.

The operation of the 16-bit counters when used in a

metering application is shown in Fig.5.

Note: If the counter value is set from 0000H to FFFFH by

software and the status 0000H was reached either by

clocking (overflow) or by hardware reset the subsequent

clock pulse (CLKx) will NOT set the interrupt flag

(C1F or C2F) in the PCCR register!

7.1

Peripheral Counter Control Register (PCCR)

Table 8

Peripheral Counter Control Register (address 40H)

Table 9

Description of PCCR bits

76543210

EC1

EC1I

C1F

EC2

EC2I

C2F

BIT

SYMBOL

DESCRIPTION

EC1

Enable Counter 1. If EC1 = 1, the counter is enabled and increments upwards every

HIGH-to-LOW transition on pin CLK1. If EC1 = 0, the incrementing stops and the

counter keeps the accumulated value. This bit is set/reset by software.

EC1I

Enable Counter 1 Interrupt Flag. When EC1I is set to a logic 1, the C1F event

requests an interrupt. This bit is set/reset by software.

not used

C1F

Counter 1 Interrupt Flag. If C1F = 1, then a counter overﬂow has occurred in

Counter 1. Set by hardware and software; reset by software.

EC2

Enable Counter 2. If EC2 = 1, the counter is enabled and increments upwards every

HIGH-to-LOW transition on pin CLK2. If EC2 = 0, the incrementing stops and the

counter keeps the accumulated value. This bit is set/reset by software.

EC2I

Enable Counter 2 Interrupt Flag. When EC2I is set to a logic 1, the C2F event

requests an interrupt. This bit is set/reset by software.

not used

C2F

Counter 2 Interrupt Flag. If C2F = 1, then a counter overﬂow has occurred in

Counter 2. Set by hardware and software; reset by software.

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