1997 Apr 16

14

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,

8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

7.1.2

The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed.

As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This

behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write

accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero.

Table 13 EEPROM Address Register (address 01H, access type R/W)

Table 14 Description of ADDR bits

7.1.3

Table 15 EEPROM Data Register (address 03H; access type R/W)

Table 16 Description of DATR bits

7.1.4

The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the

device user.

76543210

0

AD6

AD5

AD4

AD3

AD2

AD1

AD0

BIT

MNEMONIC

DESCRIPTION

7

−

This bit is set to a logic 0.

6 to 2

AD6 to AD2

AD2 to AD6 select one of 32 pages.

1 to 0

AD1 to AD0

AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and

AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0

and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment

mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1

increments after every write to an EEPROM latch, thus enhancing access to sequential

EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when

AD0 and AD1 are both a logic 1.

76543210

D7

D6

D5

D4

D3

D2

D1

D0

BIT

MNEMONIC

DESCRIPTION

7 to 0

D7 to D0

The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from

DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write

operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits AD0

and AD1 of ADDR.