PCD3755EP datasheet(16/32 Pages) PHILIPS

16 / 32 page

1997 Apr 16

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers with DTMF generator,

8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

From now on, it will be assumed that AD2 to AD6 will

contain the intended EEPROM page address after page

setup.

Table 17 Page setup; preset

Table 18 Page setup; auto-incrementing

7.5.2

READ BYTE

Since ADDR auto-increments after a read cycle regardless

of the page boundary, successive bytes can efficiently be

read by repeating the last instruction.

Table 19 Read byte

7.5.3

WRITE PAGE

The write cycle performs a logical OR between the data in

the EEPROM latches and that in the addressed EEPROM

page.

INSTRUCTION

RESULT

MOV A, #addr

address of EEPROM latch

MOV ADDR, A

send address to ADDR

MOV A, #data

load write, erase/write or erase data

MOV DATR, A

send data to addressed EEPROM

latch

INSTRUCTION

RESULT

MOV A, #MC2

increment mode control word

MOV EPCR, A

select increment mode

MOV A, #baddr

EEPROM Latch 0 address

(AD0 = AD1 = 0)

MOV ADDR, A

send EEPROM Latch 0 address to

ADDR

MOV A, R0

load 1st byte from Register 0

MOV DATR, A

send 1st byte to EEPROM Latch 0

MOV A, R1

load 2nd byte from Register 1

MOV DATR, A

send 2nd byte to EEPROM Latch 1

MOV A, R2

load 3rd byte from Register 2

MOV DATR, A

send 3rd byte to EEPROM Latch 2

MOV A, R3

load 4th byte from Register 3

MOV DATR, A

send 4th byte to EEPROM Latch 3

INSTRUCTION

RESULT

MOV A, #RDADDR load read address

MOV ADDR, A

send address to ADDR

MOV A, DATR

read EEPROM data

To actually copy the data from the EEPROM latches,

the corresponding bytes in the page should previously

have been erased.

The EEPROM latches are preset as described in

Section 7.5.1. The actual transfer to the EEPROM is then

performed as shown in Table 20.

The last instruction also starts Timer 2. The data in the

EEPROM latches are ORed with that in the corresponding

page bytes within 5 ms. A single-byte write is simply a

special case of ‘write page’.

ADDR auto-increments after the write cycle. If AD0 and

AD1 addressed EEPROM Latch 3 prior to the write cycle,

ADDR will point to the next EEPROM page (by bits AD2

to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1).

This allows efficient coding of multi-page write operations.

Table 20 Write page

7.5.4

ERASE/WRITE PAGE

The EEPROM latches are preset as described in

Section 7.5.1. The page byte corresponding to the

asserted flags (among F0 to F3) are erased and re-written

with the contents of the respective EEPROM latches.

The last instruction also starts Timer 2. Erasure takes

5 ms upon which Timer Register T2 reloads for another

5 ms cycle for writing. The top cycles together take 10 ms.

A single-byte erase/write is simply a special event of

‘erase/write page’.

ADDR auto-increments after the write cycle. If AD0 and

AD1 addressed EEPROM Latch 3 prior to the write cycle,

ADDR will point to the next EEPROM page (by AD2 to

AD6) and to EEPROM Latch 0 (by AD0 and AD1).

This allows efficient coding of multi-page erase/write

operations.

Table 21 Erase/write page

INSTRUCTION

RESULT

MOV A, #EWP + MC2

‘write page’ control word

MOV EPCR, A

start ‘write page’ cycle

INSTRUCTION

RESULT

MOV A, #EWP + MC3

‘erase/write page’ control word

MOV EPCR, A

start ‘erase/write page’ cycle

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