Philips Semiconductors

Product specification

PCK2001M

1999 Jul 06

7

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

SDRAM CLK period

1, 6

15.0

15.2

15.5

SDRAM CLK HIGH time

66MHz

2, 6, 8

5.6

7.8

8.4

ns

SDRAM CLK LOW time

3, 6, 8

5.3

7.4

8.0

SDRAM CLK period

1, 6

10.0

10.01

10.5

SDRAM CLK HIGH time

100MHz

2, 6, 8

3.3

5.1

5.7

ns

SDRAM CLK LOW time

3, 6, 8

3.1

4.9

5.5

SDRAM CLK period

1, 6

7.4

7.5

7.7

SDRAM CLK HIGH time

133MHz

2, 6, 8

2.6

3.2

3.8

ns

SDRAM CLK LOW time

3, 6, 8

2.1

2.8

3.5

SDRAM rise time

4, 6, 10

1.5

2.0

4.0

V/ns

SDRAM fall time

4, 6, 11

1.5

2.9

4.0

V/ns

SDRAM buffer LH propagation delay

6, 7

1.0

2.5

3.5

ns

SDRAM buffer HL propagation delay

6, 7

1.0

2.5

3.5

ns

SDRAM buffer enable time

6, 7

1.0

2.6

5.0

ns

SDRAM buffer disable time

6, 7

1.0

2.7

5.0

ns

DUTY CYCLE

Output Duty Cycle

Measured at 1.5V

5, 6, 7

45

52

55

%

SDRAM Bus CLK skew

1, 6

150

250

ps

Device to device skew

250

ps

NOTES:

1. Clock period and skew are measured on the rising edge at 1.5V.

5. Duty cycle should be tested with a 50/50% input.

6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.

7. Input edge rate for these tests must be faster than 1 V/ns.

8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to

ensure duty cycle specification is met.

10. Typical is measured with MAX (30pf) discrete load.

11. Typical is measured with MIN (20pf) discrete load.