AMD-K6-2ESLASH333AMZ datasheet(6/332 Pages) AMD

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Contents

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.21

EWBE# (External Write Buffer Empty) ............................... 102

5.22

FERR# (Floating-Point Error) ............................................... 103

5.23

FLUSH# (Cache Flush) .......................................................... 104

5.24

HIT# (Inquire Cycle Hit)........................................................ 105

5.25

HITM# (Inquire Cycle Hit To Modified Line)...................... 105

5.26

HLDA (Hold Acknowledge) ................................................... 106

5.27

HOLD (Bus Hold Request)..................................................... 107

5.28

IGNNE# (Ignore Numeric Exception)................................... 108

5.29

INIT (Initialization) ................................................................ 109

5.30

INTR (Maskable Interrupt).................................................... 110

5.31

INV (Invalidation Request) ................................................... 110

5.32

KEN# (Cache Enable)............................................................. 111

5.33

LOCK# (Bus Lock) .................................................................. 112

5.34

M/IO# (Memory or I/O) ........................................................... 113

5.35

NA# (Next Address)................................................................ 114

5.36

NMI (Non-Maskable Interrupt) ............................................. 114

5.37

PCD (Page Cache Disable)..................................................... 115

5.38

PCHK# (Parity Check) ........................................................... 116

5.39

PWT (Page Writethrough) ..................................................... 117

5.40

RESET (Reset) ........................................................................ 118

5.41

RSVD (Reserved).................................................................... 119

5.42

SCYC (Split Cycle).................................................................. 120

5.43

SMI# (System Management Interrupt)................................. 121

5.44

SMIACT# (System Management Interrupt Active)............. 122

5.45

STPCLK# (Stop Clock) ........................................................... 123

5.46

TCK (Test Clock)..................................................................... 124

5.47

TDI (Test Data Input) ............................................................. 124

5.48

TDO (Test Data Output)......................................................... 124

5.49

TMS (Test Mode Select) ......................................................... 125

5.50

TRST# (Test Reset)................................................................. 125

5.51

VCC2DET (VCC2 Detect) ...................................................... 126

5.52

VCC2H/L# (VCC2 High/Low)................................................. 127

5.53

W/R# (Write/Read) ................................................................. 128

5.54

WB/WT# (Writeback or Writethrough)................................. 129

5.55

Pin Tables by Type ................................................................. 130

5.56

Bus Cycle Definitions ............................................................. 132

Bus Cycles ................................................................................. 133

6.1

Timing Diagrams..................................................................... 133

6.2

Bus States................................................................................. 135

6.3

Memory Reads and Writes..................................................... 138

6.4

I/O Read and Write ................................................................. 146

6.5

Inquire and Bus Arbitration Cycles ...................................... 148

6.6

Special Bus Cycles .................................................................. 170

Power-On Configuration and Initialization ........................... 179

7.1

Signals Sampled During the Falling Transition of RESET .. 179

7.2

RESET Requirements ............................................................ 180

7.3

State of Processor After RESET............................................ 180

AMD-K6-2E/333AMZ Datasheet(PDF) 6 Page - Advanced Micro Devices

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