0.5kHz-125MHz MHz to KHz Programmable Clock

T M

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/23/07 Page 2

KEY PROGRAMMING PARAMETERS

CLK

Output Frequency

Output Drive Strength

Programmable

Input/Output

Where M=8 bit

R= 5 bit

P= 14 bit

Three optional drive strengths to

choose from:

• Low: 4mA

• Std: 8mA (default)

• High: 16mA

One output pin can be configured as:

• OE - input

• FSEL - input

• PDB – input

• CLK1 – output

• Programmable CLoad

PACKAGE PIN CONFIGURATION AND ASSIGNMENT

Pin Assignment

Name

DFN

Pin #

SC70

Pin#

SOT

Pin#

Type

Description

XIN, FIN

1

3

3

I

Crystal or Reference input pin.

GND

2

2

2

P

GND connection

CLK0

3

1

1

O

Programmable Clock Output

VDD

4

6

6

P

VDD connection

OE, PDB,

FSEL, CLK1

5

5

5

I/O

This programmable I/O pin can be configured as an Output

Enable (OE) input, Power Down input (PDB), Frequency Select

input (FSEL) or CLK1 output. This pin has an internal 60K

pull up resistor on OE, PDB and FSEL.

State

OE

PDB

FSEL

0

Tri-state CLK

Power Down Mode

Bank 0

1 (default)

Operating mode

Operating mode

Bank 1

XOUT

6

4

4

O

Crystal Output pin. Do Not Connect if FIN is used.

1

2

3

4

5

6

OE, PDB,

FSEL, CLK1

GND

XIN/FIN

CLK0

XOUT

VDD

DFN

DFN

DFN

DFN----6

6

6

6L

L

L

L

((((2

2

2

2....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....3

3

3

3mmx

mmx

mmx

mmx0

0

0

0....6

6

6

6mm

mm

mm

mm))))

SOT

SOT

SOT

SOT23

23

23

23----6

6

6

6L

L

L

L

((((3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....35

35

35

35mm

mm

mm

mm))))

1

2

3

4

5

6

VDD

CLK0

XOUT

SC

SC

SC

SC70

70

70

70----6

6

6

6L

L

L

L

((((2

2

2

2....3

3

3

3mmx

mmx

mmx

mmx2

2

2

2....25

25

25

25mmx

mmx

mmx

mmx1

1

1

1....0

0

0

0mm

mm

mm

mm))))

XIN/FIN

OE, PDB,

FSEL, CLK1

XIN/FIN

CLK0

XOUT

GND

VDD

OE,PDB,FSEL,CLK1

1

2

3

6

5

4

GND