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LTC2704 Datasheet(PDF) 5 Page - Linear Technology

No. de pieza LTC2704
Descripción Electrónicos  Quad 12-, 14- and 16-Bit Voltage Output SoftSpan DACs with Readback
PDF  20 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
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LTC2704 Datasheet(HTML) 5 Page - Linear Technology

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LTC2704
2704f
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The notation V+ is used to denote both V+1 and V+2 when the same
voltage is applied to both pins.
Note 3: Guaranteed by design, not subject to test.
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2704-16
Integral Nonlinearity (INL)
CODE
0
–1.0
–0.8
–0.4
–0.2
0
1.0
0.4
16384
32768
2704 G01
–0.6
0.6
0.8
0.2
49152
65535
V+/V– =
±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
–0.8
–0.4
–0.2
0
1.0
0.4
16384
32768
2704 G02
–0.6
0.6
0.8
0.2
49152
65535
V+/V– =
±15V
VREF = 5V
±10V RANGE
VREF (V)
–10
0.2
0.6
1.0
6
2704 G03
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0
–6
–8
–2
–4
24
8
0
10
V+/V– =
±15V
±5V RANGE
MAX
MAX
MIN
MIN
Differential Nonlinearity (DNL)
INL vs VREF
Note 4: Measured in unipolar 0V to 5V mode.
Note 5: When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay as follows:
f
tt
MAX
S
=
+
()
⎛
⎝
⎜
⎞
⎠
⎟
1
2 9
, where ts is the setup time of the receiving
device.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t11
LDAC Pulse Width
●
15
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF (Note 3)
●
50
ns
t13
CS/LD High to RFLAG High
CLOAD = 10pF (Note 3)
●
40
ns
SCK Frequency
50% Duty Cycle (Note 5)
●
40
MHz
VDD = 2.7V to 3.3V
t1
SDI Valid to SCK Setup
●
9ns
t2
SDI Valid to SCK Hold
●
9ns
t3
SCK High Time
●
15
ns
t4
SCK Low Time
●
15
ns
t5
CS/LD Pulse Width
●
12
ns
t6
LSB SCK High to CS/LD High
●
0ns
t7
CS/LD Low to SCK Positive Edge
●
12
ns
t8
CS/LD High to SCK Positive Edge
●
12
ns
t9
SRO Propagation Delay
CLOAD = 10pF
●
26
ns
t10
CLR Pulse Width
●
90
ns
t11
LDAC Pulse Width
●
20
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF
●
70
ns
t13
CS/LD High to RFLAG High
CLOAD = 10pF
●
60
ns
SCK Frequency
50% Duty Cycle (Note 5)
●
25
MHz



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