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EMF60P02JS Datasheet(PDF) 1 Page - Excelliance MOS Corp. |
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EMF60P02JS Datasheet(HTML) 1 Page - Excelliance MOS Corp. |
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1 / 6 page ![]() 2018/8/13 p.1 EMF60P02JS G S D P-Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS -20V RDSON (MAX.) 65m Ω ID -4A Pb-Free Lead Plating & Halogen Free ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNIT Gate-Source Voltage VGS ±12 V Continuous Drain Current TA = 25 °C ID -4 A TA = 70 °C -2.8 Pulsed Drain Current1 IDM -16 Power Dissipation TA = 25 °C PD 1.04 W TA = 70 °C 0.66 Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNIT Junction-to-Ambient3 RθJA (T ≤ 10sec) 83 °C / W RθJA (Steady State) 120 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1% 3The device mounted on a 1 in2 pad of 2 oz copper. |
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