PIC16F-ESLASHP datasheet(59/178 Pages) MICROCHIP

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DS40044F-page 57

PIC16F627A/628A/648A

9.2.1

CCP PIN CONFIGURATION

The user must configure the RB3/CCP1 pin as an

output by clearing the TRISB<3> bit.

9.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

9.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

9.2.4

SPECIAL EVENT TRIGGER

In this mode (CCP1M<3:0>=1011), an internal hard-

ware trigger is generated, which may be used to initiate

an action. See Register 9-1.

The special event trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and CCPR1H, CCPR1L register

pair. The TMR1H, TMR1L register pair is not reset until

the next rising edge of the TMR1 clock. This allows the

CCPR1 register pair to effectively be a 16-bit program-

mable period register for Timer1. The special event

trigger output also starts an A/D conversion provided

that the A/D module is enabled.

TABLE 9-2:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Note:

Clearing the CCP1CON register will force

the RB3/CCP1 compare output latch to

the default low level. This is not the data

latch.

Note:

Removing the match condition by chang-

ing the contents of the CCPR1H, CCPR1L

generates the special event trigger and

the clock edge that generates the TMR1

Reset will preclude the

Reset from

occuring.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

PIR1

EEIF CMIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF 0000 -000 0000 -000

8Ch

PIE1

EEIE CMIE

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE 0000 -000 0000 -000

86h, 186h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

10h

T1CON

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h

CCPR1L

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

CCP1X

CCP1Y

CCP1M3

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.

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