| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
DSPIC30F2011 Datasheet(PDF) 83 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
DSPIC30F2011 Datasheet(HTML) 83 Page - Microchip Technology |
|
83 / 205 page ![]() © 2006 Microchip Technology Inc. DS70139E-page 81 dsPIC30F2011/2012/3012/3013 11.0 INPUT CAPTURE MODULE This section describes the input capture module and associated operational modes. The features provided by this module are useful in applications requiring fre- quency (period) and pulse measurement. Figure 11-1 depicts a block diagram of the input cap- ture module. Input capture is useful for such modes as: • Frequency/Period/Pulse Measurements • Additional Sources of External Interrupts Important operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels. 11.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits, ICM<2:0> (ICxCON<2:0>). 11.1.1 CAPTURE PRESCALER There are four input capture prescaler settings speci- fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the capture channel is turned off, the prescaler counter is cleared. In addition, any Reset clears the prescaler counter. FIGURE 11-1: INPUT CAPTURE MODE BLOCK DIAGRAM Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ICxBUF Prescaler ICx pin ICM<2:0> Mode Select 3 Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channel (1 or 2). 10 Set Flag ICxIF ICTMR T2_CNT T3_CNT Edge Detection Logic Clock Synchronizer 1, 4, 16 From GP Timer Module 16 16 FIFO R/W Logic ICI<1:0> ICBNE, ICOV ICxCON Interrupt Logic Set Flag ICxIF Data Bus |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |