7 Detailed Description

7.1 Overview

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding

clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When

high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each

clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs

on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on

the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a

clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low

enables the other clock input. This allows the system clock to be free running, and the register can be stopped

on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Function Table

INPUTS

OUTPUTS

INTERNAL

QH

CLR

SH/LD

CLK INH

CLK

SER

PARALLEL

A...H

QA

QB

L

X

X

X

X

X

L

L

L

H

X

L

L

X

X

QA0

QB0

QH0

H

L

L

↑

X

a...h

a

b

h

H

H

L

↑

H

X

H

QAn

QGn

H

H

L

↑

L

X

L

QAn

QGn

H

X

H

↑

X

X

QA0

QB0

QH0

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SN54HC166, SN74HC166

SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022

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