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ADPL44002ACPZN2.5-R7 Datasheet(PDF) 8 Page - Analog Devices

No. de pieza ADPL44002ACPZN2.5-R7
Descripción Electrónicos  40V, 200mA, Low Noise, CMOS LDO Linear Regulator
PDF  23 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADPL44002ACPZN2.5-R7 Datasheet(HTML) 8 Page - Analog Devices

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Data Sheet
ADPL44002
analog.com
Rev. 0
8 of 23
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 6-Lead LFCSP Pin Configuration
Figure 4. 5-Lead TSOT Pin Configuration
Pin Descriptions
Table 5. Pin Descriptions
PIN
NAME
DESCRIPTION
6-LEAD
LFCSP
5-LEAD
TSOT
1
5
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 2.2µF or
greater capacitor.
2
4
SENSE/ADJ
Sense Input (SENSE). Connect to load. An external resistor divider
may also be used to set the output voltage higher than the fixed
output voltage (ADJ).
3
2
GND
Ground.
4
3
EN
The Enable Pin Controls the operation of the LDO. Drive EN high to
turn on the regulator. Drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
5
Not
applicable
SS
Soft Start. An external capacitor connected to this pin determines
the soft-start time. Leave this pin open for a typical 400μs start-up
time. Do not ground this pin.
6
1
VIN
Regulator Input Supply. Bypass VIN to GND with a 2.2µF or greater
capacitor.
EP
Exposed Pad. The exposed pad on the bottom of the package
enhances thermal performance and is electrically connected to
GND inside the package. It is recommended that the exposed pad
connect to the ground plane on the board.
3
GND
1
VOUT
2
SENSE/ADJ
4 EN
6 VIN
5 SS
ADPL44002
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE
PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED
PAD CONNECT TO THE GROUND PLANE ON THE BOARD.
ADPL44002
TOP VIEW
(Not to Scale)
1
VIN
2
GND
3
EN
5
VOUT
4
SENSE/ADJ



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