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HT48C062 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT48C062 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 31 page ![]() HT48R062/HT48C062 Rev. 1.11 9 October 30, 2006 Input/Output Ports There are up to 11 bidirectional input/output lines in the microcontroller labeled with port names PA and PB, which are mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H or 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the con- trol register must write ²1². The input source also de- pends on the control register. If the control register bit is ²1², the input will read the pad state. If the control regis- ter bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify- write ² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H and 15H. The chip reset status of the registers is summarized in the following table: Register Reset (Power-on) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* Program Counter 000H 000H 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu PBC ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu Note: ²*² means ²warm reset² ²u² means ²unchanged² ²x² means ²unknown² V D D P A 0 ~ P A 7 P B 0 ~ P B 2 M U X W a k e - u p O p t i o n S y s t e m W a k e - u p ( P A o n l y ) R e a d D a t a R e g i s t e r D Q C K S C o n t r o l B i t P u l l - h i g h D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e D a t a R e g i s t e r D a t a B i t Q D Q C K S Q Input/Output Ports |
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