MSC7116 datasheet(23/56 Pages) FREESCALE

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Electrical Characteristics

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

Freescale Semiconductor

2.5.2.3

Multiplication Factor Range

The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.

2.5.2.4

Allowed Core Clock Frequency Range

The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown

in Table 11.

This bit along with the CKSEL determines the frequency range of the core clock.

2.5.2.5

Core Clock Frequency Range When Using DDR Memory

The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this

restriction.

Table 10. PLLMLTF Ranges

Multiplier Block (Loop) Output Range

Minimum PLLMLTF Value

Maximum PLLMLTF Value

266

≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz

266/Divided Input Clock

532/Divided Input Clock

Note:

This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the

frequency of the Divided Input Clock.

Table 11. Fvco Frequency Ranges

CLKCTRL[RNG] Value

Allowed Range of Fvco

266

≤ Fvco ≤ 532 MHz

133

≤ Fvco ≤ 266 MHz

Note:

This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG].

Table 12. Resulting Ranges Permitted for the Core Clock

CLKCTRL[CKSEL]

CLKCTRL[RNG]

Resulting

Division

Factor

Allowed Range

of Core Clock

Comments

Reserved

133

≤ core clock ≤ 266 MHz

Limited by range of PLL

133

≤ core clock ≤ 266 MHz

Limited by range of PLL

66.5

≤ core clock ≤ 133 MHz

Limited by range of PLL

Note:

This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL].

Table 13. Core Clock Ranges When Using DDR

DDR Type

Allowed Frequency

Range for DDR CK

Corresponding Range

for the Core Clock

Comments

DDR 200 (PC-1600)

83–100 MHz

166

≤ core clock ≤ 200 MHz

Core limited to 2

× maximum DDR frequency

DDR 266 (PC-2100)

DDR 333 (PC-2600)

83–133 MHz

166

≤ core clock ≤ 266 MHz

Core limited to 2

× maximum DDR frequency

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