RT9232BGS datasheet(13/14 Pages) RICHTEK

13 / 14 page

RT9232B

DS9232B-03

March 2007

www.richtek.com

Feedback Loop Design Procedure

Use these guidelines for locating the poles and zeros of

the compensation network :

1. Pick Gain (R2/R1) for desired 0dB crossing frequency

(FC).

2. Place 1ST zero FZ1 below modulator's double pole FLC

(~75% FLC).

3. Place 2ND zero FZ2 at modulator's double pole FLC.

4. Place 1ST pole FZ1 at the ESR zero FZ_ESR.

5. Place 2ND pole FZ2 at half the switching frequency.

6. Check gain against error amplifier's open-loop gain.

7. Pick RFB for desired output voltage.

8. Estimate phase margin and repeat if necessary.

Layout Consideration

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability. First, place the PWM power stage components.

Mount all the power components and connections in the

top layer with wide copper areas. The MOSFETs of Buck,

inductor, and output capacitor should be as close to each

other as possible. This can reduce the radiation of EMI

due to the high frequency current loop. If the output

capacitors are placed in parallel to reduce the ESR of

capacitor, equal sharing ripple current should be

considered. Place the input capacitor directly to the drain

of high-side MOSFET. The MOSFETs of linear regulator

should have wide pad to dissipate the heat. In multilayer

PCB, use one layer as power ground and have a separate

control signal ground as the reference of the all signal. To

avoid the signal ground is effect by noise and have best

load regulation, it should be connected to the ground

terminal of output. Furthermore, follows below guidelines

can get better performance of IC :

(1). The IC needs a bypassing ceramic capacitor as a R-C

filter to isolate the pulse current from power stage

and supply to IC, so the ceramic capacitor should be

placed adjacent to the IC.

(2). Place the high frequency ceramic decoupling close

to the power MOSFETs.

(3). The feedback part should be placed as close to IC as

possible and keep away from the inductor and all noise

sources.

(4). The components of bootstraps should be closed to

each other and close to MOSFETs.

(5).The PCB trace from Ug and Lg of controller to

MOSFETs should be as short as possible and can

carry 1A peak current.

(6). Place all of the components as close to IC as possible.

100

10K

100K

10M

-60

-40

-20

100

Modulator

Gain

ESR

Closed Loop Gain

Compensation

Gain

Open Loop Error

AMP Gain

20LOG

(VIN/ΔVOSC)

20LOG

(R1/R2)

Z1 FZ2

Frequency (Hz)

Figure 3

RT9232BGS Datasheet(PDF) 13 Page - Richtek Technology Corporation

RT9232BGS Datasheet(HTML) 13 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Descarga

Enlace URL