LP55271TLX datasheet(17/21 Pages) NSC

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2C Compatible Interface (Continued)

Bus Free Time between a STOP and a START Condition

1.3

µs

Capacitive Load for Each Bus Line

200

NOTE: Data guaranteed by design

Test Interface

The test bus can be controlled externally or internally. For

the external control, the LP55271 pins V

DD1,2 only need to

be powered. External control is independent on status of

NRST and V

DDIO pins. T1 is an input and it has an internal 6

Ω pull-down resistor. T2 is an output line for the test result

with an internal 200 k

Ω pull-down resistor. When T1 is low,

T2 is always pulled down; when T1 is high, T2 is indicating

the result of the test.

20202419

High Level Schematic Representation of the Test Interface

The device is capable of detecting a defective unit in three

cases:

•

Production test 1: The LP55271 is assembled on a

printed wiring board (PWB), but there is no LEDs con-

nected on current sink outputs. An external 4.2V test

voltage is supplied on the V

DD1 and VDD2 pins, from

which follows that the reset operating mode is entered

with POR. Test pin T1 is pulled high. The chip will send an

acknowledge “1” onto the T2 pin if the chip is in working

order; otherwise T2 stays low (0). Refer to Test Interface

Timing Diagram.

•

Production test 2: The LP55271 is assembled on a

PWB with the external components shown in LP55271

Block Diagram. 4.2V voltage is connected to V

DD1,VDD2

and FB pins (see the figure above), from which follows

that the reset operating mode is entered with POR. Test

pin T1 is pulled high. The chip will send an acknowledge

“1” onto the T2 pin if the chip is in working order; other-

wise T2 stays low (0). If the ACK is “1”, a repetitive test

pattern “0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and

if the LED corresponding the pattern (see Test Interface

Timing Diagram) is connected properly T2 gives “1”, oth-

erwise T2 stays low. The last “1” disengages the test.

•

Field test: Build-in self-test through the I

2C compatible

control interface. The LP55271 is enabled (NSTBY(bit) =

1, EN_BOOST(bit) = 1) and external test pins T1 and T2

are disconnected. The result can be read through the I

compatible control interface. LED test is enabled by writ-

ing to address 0Ch hex data 01h. Result can be read

from the same address during the next I

2C cycle. Note:

2C compatible interface clock signal controls the timing

of the test procedure. For that reason the clock signal

frequency should be 50 kHz or less during the build-in

self-test.

LP55271TLX Datasheet(PDF) 17 Page - National Semiconductor (TI)

LP55271TLX Datasheet(HTML) 17 Page - National Semiconductor (TI)

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