M41T256YMT7F datasheet(18/30 Pages) STMICROELECTRONICS

18 / 30 page

Clock operation

M41T256Y

18/30

Table 3.

TIMEKEEPER® register map

Keys:

S = Sign bit

FT = Frequency test bit

ST = Stop bit

WC = Write clock bit

X = '1' or '0'

BL = Battery low flag (read only bit)

TB = Tamper bit (read only bit)

TEB = Tamper enable bit

0 = Must be set to '0'

SLP = Sleep mode bit

Note:

7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.

3.4

Power-on reset

The M41T256Y continuously monitors VCC. When VCC falls to the power fail detect trip

point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC

passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor

should be chosen to control rise time.

Address

Data

Function/Range

BCD Format

7FFFh

10 years

Year

00-99

7FFEh

10M

Month

01-12

7FFDh

10 date

Date: Day of Month

Date

01-31

7FFCh

TEB

Day of Week

Tamper/day

0-1/01-07

7FFBh

10 hours

Hours (24 Hour Format)

Hours

00-23

7FFAh

10 minutes

Minutes

00-59

7FF9h

10 seconds

Seconds

00-59

7FF8h

SLP

Calibration

Control

7FF7h

0.1 Seconds

0.01 Seconds

Seconds

00-99

7FF6h

XXXXX

XXX

Reserved

7FF5h

XXXXX

XXX

Reserved

7FF4h

XXXXX

XXX

Reserved

7FF3h

XXXXX

XXX

Reserved

7FF2h

XXXXX

XXX

Reserved

7FF1h

XXXXX

XXX

Reserved

7FF0h

XXXXX

XXX

Reserved

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