DS1921G datasheet(3/45 Pages) DALLAS

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DS1921G Thermochron iButton

Figure 1. DS1921G BLOCK DIAGRAM

Internal

Timekeeping &

Control Reg. &

Counters

3V Lithium

General-Purpose

SRAM

Alarm Time Stamp

and Duration

Logging Memory

Datalog

Memory

Histogram Memory

32.768kHz

Oscillator

Control

Logic

Temperature

Core

256-Bit

Scratchpad

Memory

Function

Control

ROM

Function

Control

64-Bit

Lasered

ROM

Parasite

Powered

Circuitry

1-Wire

Port

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power when-

ever the IO input is high. IO will provide sufficient power as long as the specified timing and voltage re-

quirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium

is conserved, and 2) if the lithium is exhausted for any reason, the ROM may still be read normally.

64-BIT LASERED ROM

Each DS1921G contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. See

Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift

8 + X5+ X4 + 1. Additional information

about the Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27 and in the Book of

DS19xx iButton Standards.

The shift register bits are initialized to 0. Then starting with the least significant bit of the family code,

one bit at a time is shifted in. After the eighth bit of the family code has been entered, then the serial

number is entered. After the 48

th bit of the serial number has been entered, the shift register contains the

CRC value. Shifting in the eight bits of CRC returns the shift register to all 0s.

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