TMP93CS32F datasheet(21/180 Pages) TOSHIBA

21 / 180 page

TMP93CS32

2004-02-10

93CS32-19

(3) Operation

1. RUN mode

In the RUN mode, the system clock continues to operate even after a HALT

instruction is executed. Only the CPU stops executing the instruction.

In the halt state, an interrupt request is sampled with the falling edge of the

“CLK” signal.

Releasing the RUN mode is executed by the external/internal interrupts. (See

Table 3.3.3 Halt Releasing Source and Halt Releasing Operation.)

Figure 3.3.6 shows the interrupt timing for releasing the halt state by

interrupts in the RUN/IDLE2 mode.

Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes

2. IDLE2 mode

In the IDLE2 mode, the system clock is supplied to only specific internal I/O

devices, and the CPU stops executing the current instruction.

In the IDLE2 mode, the halt state is released by an interrupt with the same

timing as in the RUN mode. The IDLE2 mode is released by external/internal

interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.3 Halt Releasing

Source and Halt Releasing Operation.)

In the IDLE2 mode, the watchdog timer should be disabled before entering the

halt status to prevent the watchdog timer interrupt occurring just after releasing

the HALT mode.

Address

Data

RUN/IDLE2

mode

CLK

A0 to A23

ALE

AD0 to AD15

NMI

INT0

(Level)

INT4 to INT7

(Rising edge)

INT4, INT6

(Falling edge)

Internal INT

Address

+ 2

Address

Data

TMP93CS32F Datasheet(PDF) 21 Page - Toshiba Semiconductor

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