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DSP56321 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc |
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DSP56321 Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 84 page  AC Electrical Characteristics DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 2-21 2.4.7 SCI Timing Table 2-11. SCI Timings No. Characteristics1 Symbol Expression 200 MHz 220 MHz 240 MHz 275 MHz Uni t Min Max Min Max Min Max Min Max 400 Synchronous clock cycle tSCC 2 16 × TC 80.0 — 72.8 — 66.7 — 58.0 — ns 401 Clock low period tSCC/2 −10.0 30.0 — 26.4 — 23.4 — 19.0 — ns 402 Clock high period tSCC/2 −10.0 30.0 — 26.4 — 23.4 — 19.0 — ns 403 Output data setup to clock falling edge (internal clock) tSCC/4 + 0.5 × TC −17.0 5.5 — 3.5 — 1.76 — –0.68 — ns 404 Output data hold after clock rising edge (internal clock) tSCC/4 −1.5 × TC 13 — 11.5 — 10 — 9.04 — ns 405 Input data setup time before clock rising edge (internal clock) tSCC/4 + 0.5 × TC + 25.0 47.5 — 45.5 — 43.8 — 41.32 — ns 406 Input data not valid before clock rising edge (internal clock) tSCC/4 + 0.5 × TC −5.5 — 17.0 — 15.0 — 13.8 — 10.81 ns 407 Clock falling edge to output data valid (external clock) — 32.0 — 32.0 — 32.0 — 32.0 ns 408 Output data hold after clock rising edge (external clock) TC + 8.0 13.0 — 12.6 — 12.2 — 11.64 — ns 409 Input data setup time before clock rising edge (external clock) 0.0 — 0.0 — 0.0 — 0.0 — ns 410 Input data hold time after clock rising edge (external clock) 9.0 — 9.0 — 9.0 — 9.0 — ns 411 Asynchronous clock cycle tACC 3 64 × TC 320.0 — 291.2 — 266.9 — 232.0 — ns 412 Clock low period tACC/2 −10.0 150.0 — 135.6 — 123.5 — 106.0 — ns 413 Clock high period tACC/2 −10.0 150.0 — 135.6 — 123.5 — 106.0 — ns 414 Output data setup to clock rising edge (internal clock) tACC/2 −30.0 130.0 — 115.6 — 103.5 — 86.0 — ns 415 Output data hold after clock rising edge (internal clock) tACC/2 −30.0 130.0 — 115.6 — 103.5 — 86.0 — ns Notes: 1. VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF. 2. tSCC = synchronous clock cycle time (for internal clock, tSCC is determined by the SCI clock control register and TC). 3. tACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, tACC is determined by the SCI clock control register and TC). 4. In the timing diagrams that follow, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity is programmable in the SCI Control Register (SCR). Refer to the DSP56321 Reference Manual for details. |
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