Data Sheet

ADPL40502

analog.com

Rev. 0

15 of 17

OUTLINE DIMENSIONS

Figure 29. 5-Lead, Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters

Figure 30. 6-Lead, Lead Frame Chip Scale Package [LFCSP] 2mm × 2mm Body and 0.55mm Package Height (CP-6-3)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-193-AB

0.95 BSC

1.90 REF

0.90

0.70

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

1.00 MAX

5

4

1

2

3

END VIEW

TOP VIEW

SIDE VIEW

3.05

2.90

2.75

3.05

2.80

2.55

1.75

1.60

1.45

SEATING

PLANE

1.70

1.60

1.50

0.425

0.350

0.275

TOP VIEW

6

1

4

3

0.35

0.30

0.25

BOTTOM VIE W

PIN 1 INDEX

AREA

0.60

0.55

0.50

1.10

1.00

0.90

0.20 REF

0.05 MAX

0.02 NOM

0.65 BSC

EXPOSED

PAD

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

2.10

2.00 SQ

1.90

0.15 MIN

SEATING

PLANE

PIN1

INDIC ATORAREAOPTIONS

(SEEDETAILA)

DETAIL A

(JEDEC 95)