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SWITCHING CHARACTERISTICS

PARAMETER MEASUREMENT INFORMATION

GND

V

DD

R=60 W

V

Yx

R=60 W

V

/2

DD

V

Yx

CDCVF855

S0229-02

CDCVF855

SCAS839A – APRIL 2007 – REVISED MAY 2007

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low- to high-level propagation delay

tPLH(1)

Test mode/CLK to any output

3.5

ns

time

High- to low-level propagation delay

tPHL (1)

Test mode/CLK to any output

3.5

ns

time

100/133/167 MHz

–65

65

(PC1600/2100/2700)

tjit(per)(2)

Jitter (period), see Figure 7

ps

200 MHz (PC3200)

–30

30

100/133/167 MHz

–60

60

(PC1600/2100/2700)

tjit(cc)(2)

Jitter (cycle-to-cycle), see Figure 4

ps

200 MHz (PC3200)

–40

40

100/133/167 MHz

–100

100

(PC1600/2100/2700)

tjit(hper)(2)

Half-period jitter, see Figure 8

ps

200 MHz (PC3200)

–75

75

tslr(o)

Output clock slew rate, see Figure 9

Load: 120

Ω, 14 pF

1

2

V/ns

t(φ)

Static phase offset, see Figure 5

100/133/167/200 MHz

–50

50

ps

Load: 120

Ω, 14 pF;

tsk(o)

Output skew, see Figure 6

40

ps

100/133/167/200 MHz

(1)

Refers to the transition of the noninverting output.

(2)

This parameter is assured by design but cannot be 100% production tested.

Figure 1. IBIS Model Output Load

6

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