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VLSI
Solution
y
VS1103b
VS1103B
6. FUNCTIONAL DESCRIPTION
2 In addition, the cycles spent in the user application routine must be counted.
3 Firmware changes the value of this register immediately after reset to 0x38, and in less than 100 ms to
0x30.
4 When mode register write specifies a software reset the worst-case time is 16600 XTALI cycles.
5 Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not a
good idea to send SCI or SDI bits while this register update is in progress.
Note: it is not allowed to do an SCI operation while DREQ is low. If this is done, however, DREQ stays
low even after the SCI operation has been processed.
6.6.1 SCI MODE (RW)
SCI MODE is used to control the operation of VS1103b and defaults to 0x0800 (SM SDINEW set).
SCI MODE bits
Name
Bit
Function
Value
Description
SM DIFF
0
Differential
0
normal in-phase audio
1
left channel inverted
SM RECORD PATH
1
Choose ADPCM recording
0
A/D stream
path
1
Mixer output
SM RESET
2
Soft reset
0
no reset
1
reset
SM OUTOFMIDI
3
Cancel MIDI decoding
0
no
1
yes
SM PDOWN
4
Powerdown
0
power on
1
powerdown
SM TESTS
5
Allow SDI tests
0
not allowed
1
allowed
SM ICONF
7:6
Input configuration
0
SDI MIDI, SCI ADPCM
1
SCI MIDI, SDI ADPCM
2
UART RT-MIDI, SCI ADPCM
3
UART RT-MIDI, SDI ADPCM
SM DACT
8
DCLK active edge
0
rising
1
falling
SM SDIORD
9
SDI bit order
0
MSb first
1
MSb last
SM SDISHARE
10
Share SPI chip select
0
no
1
yes
SM SDINEW
11
VS1002 native SPI modes
0
no
1
yes
SM EARSPEAKER
13:12
Earspeaker setting
0
off
1
low
2
mid
3
high
SM LINE IN
14
A/D stream input
0
microphone
selector
1
line in
SM ADPCM
15
ADPCM recording active
0
no
1
yes
Version 1.01, 2007-09-03
29
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