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LCZP Datasheet(PDF) 14 Page - Linear Technology

No. de pieza LCZP
Descripción Electrónicos  16-/14-/12-Bit VOUT DACs in 3mm3mm DFN
PDF  20 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
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LCZP Datasheet(HTML) 14 Page - Linear Technology

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LTC2641/LTC2642
14
26412f
APPLICATIONS INFORMATION
Unbuffered Operation and VOUT Loading
The DAC output is available directly at the VOUT pin, which
swings from GND to VREF. Unbuffered operation provides
the lowest possible offset, full-scale and linearity errors, the
fastest settling time and minimum power consumption.
However, unbuffered operation requires that appropriate
loading be maintained on the VOUT pin. The LTC2641/
LTC2642 VOUT can be modeled as an ideal voltage source
in series with a source resistance of ROUT, typically 6.2k
(Figure 4). The DAC’s linear output impedance allows
it to drive medium loads (RL > 60k) without degrading
INL or DNL; only the gain error is increased. The gain
error (GE) caused by a load resistance, RL, (relative to
full scale) is:
GE
R
R
OUT
L
=
+
⎝⎜
⎠⎟
–1
1
In 16-bit LSBs:
GE
R
R
LSB
OUT
L
=
+
⎝⎜
⎠⎟
[]
–65536
1
ROUT has a low tempco (typically < ±50ppm/°C), and is
independent of DAC code. The variation of ROUT, part-to-
part, is typically less than ±20%.
Note on LSB units:
For the following error descriptions, “LSB” means 16-bit
LSB and 65,536 is rounded to 66k.
To convert to 14-bit LSBs (LTC2641-14/LTC2642-14)
divide by 4.
To convert to 12-bit LSBs (LTC2641-12/LTC2642-12)
divide by 16.
A constant current, IL, loading VOUT will produce an offset
of:
VOFFSET = –IL • ROUT
For VREF = 2.5V, a 16-bit LSB equals 2.5V/65,536, or 38μV.
Since ROUT is 6.2k, an IL of 6nA produces an offset of
1LSB. Therefore, to avoid degrading DAC performance,
it is critical to protect the VOUT pin from any sources of
leakage current.
Unbuffered VOUT Settling Time
The settling time at the VOUT pin can be closely approxi-
mated by a single-pole response where:
τ = ROUT • (COUT + CL)
(Figure 4). Settling to 1/2LSB at 16-bits requires about
12 time constants (ln(2 • 65,536)). The typical settling
time of 1μs corresponds to a time constant of 83ns, and
a total (COUT + CL) of about 83ns/6.2k = 13pF. The internal
capacitance, COUT is typically 10pF, so an external CL of
3pF corresponds to 1μs settling to 1/2LSB.
IL
VOUT
0V TO VREF
ROUT
VOUT
COUT
LTC2641
LTC2642
VREF
REF
GND
CODE
2N
VREF
()
CL
26412 F04
RL
+
Figure 4. VOUT Pin Equivalent Circuit
Op Amp Selection
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
In bipolar mode (LTC2642 only), the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. In this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
±VREF output range (Figure 3).
In unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applica-
tions a precision, rail-to-rail input, single supply op amp



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