SX28ACSLASHDP datasheet(13/51 Pages) PARALLAX

13 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 13 of 51

Rev 1.6 11/20/2006

4.0

SPECIAL-FUNCTION REGISTERS

The CPU uses a set of special-function registers to control

the operation of the device.

The CPU registers include an 8-bit working register (W),

which serves as a pseudo accumulator. It holds the second

operand of an instruction, receives the literal in immediate

type instructions, and also can be program selected as the

destination register.

A set of 31 file registers serves as the primary

accumulator. One of these registers holds the first operand

of an instruction and another can be program-selected as

the destination register. The first eight file registers

include the Real-Time Clock/Counter register (RTCC),

the lower eight bits of the 11-bit Program Counter (PC),

the 8-bit STATUS register, three port control registers for

Port A, Port B, Port C, the 8-bit File Select Register

(FSR), and INDF used for indirect addressing.

The five low-order bits of the FSR register select one of

the 31 file registers in the indirect addressing mode.

Calling for the file register located at address 00h (INDF)

in any of the file-oriented instructions selects indirect

addressing, which uses the FSR register. It should be

noted that the file register at address 00h is not a

physically implemented register. The CPU also contains

an 8 level, 11-bit hardware push/pop stack for subroutine

linkage.

Table 4-1: Special-Function Register

Address

Name

Function

00h

INDF

Used for indirect addressing

01h

RTCC

Real Time Clock/Counter

02h

Program Counter (low byte)

03h

STATUS

Holds status bits of ALU

04h

FSR

File Select Register

05h

Port RA control register

06h

Port RB control register

07h

RC*

Port RC control register

*In the SX20 package, Port C is not used, and address 07h is

available as a general-purpose RAM location.

4.1.

PC Register (02h)

The PC register holds the lower eight bits of the program

counter. It is accessible at run time to perform branch

operations.

4.2.

STATUS Register (03h)

The STATUS register holds the arithmetic status of the

ALU, the page select bits, and the reset state. The

STATUS register is accessible during run time, except

that bits PD and TO are read-only. It is recommended that

only SETB and CLRB instructions be used on this

STATUS register as the ALU status bits are updated upon

completion of the write operation, possibly leaving the

STATUS register with a result that is different than

intended.

PA2

PA1

PA0

Bit 7

Bit 0

Bit 7-5: Page select bits PA2:PA0

000 = Page 0 (000h - 01FFh)

001 = Page 1 (200h - 03FFh)

010 = Page 2 (400h - 05FFh)

011 = Page 3 (600h - 07FFh)

Bit 4:

Time Out bit, TO

1 = Set to 1 after power up and upon execution

of CLRWDT or SLEEP instructions

0 = A watchdog time-out occurred

Bit 3:

Power Down bit, PD

1= Set to a 1 after power up and upon execution

of the CLRWDT instruction

0 = Cleared to a ‘0’ upon execution of SLEEP

instruction

Bit 2:

Zero bit, Z

1 = Result of math operation is zero

0 = Result of math operation is non-zero

Bit 1:

Digit Carry bit, DC

After Addition:

1 = A carry from bit 3 occurred

0 = No carry from bit 3 occurred

After Subtraction:

1 = No borrow from bit 3 occurred

0 = A borrow from bit 3 occurred

Bit 0:

Carry bit, C

After Addition:

1 = A carry from bit 7 of the result occurred

0 = No carry from bit 7 of the result occurred

After Subtraction:

1 = No borrow from bit 7 of the result occurred

0 = A borrow from bit 7 of the result occurred

Rotate (RR or RL) Instructions:

The carry bit is loaded with the low or high order

bit, respectively. When CF bit is cleared, Carry

bit works as input For ADD and SUB

instructions.

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