WM8994ECSSLASHR datasheet(135/363 Pages) CIRRUS

135 / 363 page

WM8994

Rev 4.6

135

Note that the charge pump clock is derived from internal clock SYSCLK; either MCLK or the FLL

output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal

must be present for the charge pump to function. However, the FLL has a free-running mode that

does not require an external clock but will generate an internal clock suitable for running the charge

pump. The clock division from SYSCLK is handled transparently by the WM8994 without user

intervention, as long as SYSCLK

and sample rates are set correctly. Refer to the “Clocking and

Sample Rates

” section for more detail on the FLL and clocking configuration.

When the Charge Pump is disabled, the output can be left floating or can be actively discharged,

depending on the CP_DISCH control bit.

If the headphone output drivers (HPOUT1L and HPOUT1R) are not used, then the Charge Pump and

the associated external components are not required. The Charge Pump and Headphone drivers

should not be enabled in this case (CP_ENA=0, HPOUT1L_ENA=0, HPOUT1R_ENA=0).

If the Charge Pump is not used, and the associated external components are omitted, then the CPCA

and CPCB pins can be left floating; the CPVOUTP and CPVOUTN pins should be grounded as

illustrated in Figure 33.

Note that, when the Charge Pump is disabled, it is still recommended that the CPVDD pin is kept

within its recommended operating conditions (1.71V to 2.0V).

CPVDD

WM8994

Charge Pump

(Disabled)

CP_ENA = 0

CPVOUTP

CPVOUTN

CPCA

CPCB

CPGND

Figure 33 External Configuration when Charge Pump not used

WM8994ECS/R Datasheet(PDF) 135 Page - Cirrus Logic