WM8994ECSSLASHR datasheet(158/363 Pages) CIRRUS

158 / 363 page

WM8994

158

Rev 4.6

DIGITAL CORE FIFO ERROR STATUS DETECTION

The WM8994 monitors the Digital Core for error conditions which may occur if a clock rate mismatch

is detected. Under these conditions, the digital audio may become corrupted.

The most likely cause of a Digital Core FIFO Error condition is an incorrect system clocking

configuration. See “Clocking and Sample Rates” for the WM8994 system clocking requirements.

The Digital Core FIFO Error function is provided in order that the system configuration can be verified

during product development.

The FIFO Error signal may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The FIFO Error signal is an input to the Interrupt control circuit. An interrupt event is triggered on the

rising edge of the FIFO Error signal. The associated interrupt bit is latched once set; it can be polled at

any time or used to control the

IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

OPCLK CLOCK OUTPUT

A clock output (OPCLK) derived from SYSCLK may be output on any GPIO pin by setting the

respective GPIO registers as described in

“GPIO Control”. This clock is enabled by register bit

OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.

See “Clocking and Sample Rates” for more details of the System Clock (SYSCLK).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (0002h)

Power

Management

(2)

OPCLK_EN

GPIO Clock Output (OPCLK) Enable

0 = Disabled

1 = Enabled

R521 (0209h)

Clocking 1

2:0

OPCLK_DIV

000

GPIO Output Clock (OPCLK) Divider

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Table 85 OPCLK Control

FLL CLOCK OUTPUT

The FLL Clock outputs may be output directly on any GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the WM8994 system clocking and for details of

how to enable and configure the Frequency Locked Loops.

WM8994ECS/R Datasheet(PDF) 158 Page - Cirrus Logic

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