LAN9252SLASHML datasheet(92/329 Pages) MICROCHIP

92 / 329 page

LAN9252

DS00001909A-page 92

 2015 Microchip Technology Inc.

9.5.6.2

Index Register Data Access

The figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit

modes.

16-BIT READ AND WRITE

For writes, the address is set to access the lower WORD of one of the Index Registers. Data on D[15:0] is written on

the trailing edge of WR. The cycle repeats for the upper WORD of the Index Register, if desired by the host.

For reads, the address is set to access the lower WORD of one of the Index Registers. Read data is driven on D[15:0]

during RD active. The cycle repeats for the upper WORD of the Index Register, if desired by the host.

8-BIT READ AND WRITE

For writes, the address is set to access the lower BYTE of one of the Index Registers. Data on D[7:0] is written on the

trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Reg-

ister, if desired by the host.

For reads, the address is set to access the lower BYTE of one of the Index Registers. Read data is driven on D[7:0]

during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs of the Index Register,

if desired by the host.

Note:

The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to that WORD

are not useful.

FIGURE 9-27:

INDEXED ADDRESSING INDEX REGISTER ACCESS - 16-BIT WRITE/READ

INDEX,1'b0

Index 15:8

D[15:8]

A[4:1]

INDEX,1'b1

8'hXX

Index 7:0

D[7:0]

8'hXX

INDEX,1'b0

Index 15:8

Index 7:0

INDEX,1'b1

8'hXX

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