LAN9252VSLASHPT datasheet(7/329 Pages) MICROCHIP

7 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 7

LAN9252

1.3

TABLE 1-3:

Read:

A register or bit with this attribute can be read.

Read:

A register or bit with this attribute can be written.

Read only:

Read only. Writes have no effect.

Write only:

If a register or bit is write-only, reads will return unspecified data.

Write One to Clear:

Writing a one clears the value. Writing a zero has no effect

WAC

Write Anything to Clear:

Writing anything clears the value.

Read to Clear:

Contents is cleared after the read. Writes have no effect.

Latch Low:

Clear on read of register.

Latch High:

Clear on read of register.

Self-Clearing:

Contents are self-cleared after the being set. Writes of zero have no

effect. Contents can be read.

Self-Setting:

Contents are self-setting after being cleared. Writes of one have no

effect. Contents can be read.

RO/LH

Read Only, Latch High:

Bits with this attribute will stay high until the bit is read. After it

is read, the bit will either remain high if the high condition remains, or will go low if the

high condition has been removed. If the bit has not been read, the bit will remain high

regardless of a change to the high condition. This mode is used in some Ethernet PHY

registers.

NASR

Not Affected by Software Reset.

The state of NASR bits do not change on assertion

of a software reset.

RESERVED

Reserved Field:

Reserved fields must be written with zeros to ensure future compati-

bility. The value of reserved bits is not guaranteed on a read.

LAN9252V/PT Datasheet(PDF) 7 Page - Microchip Technology

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