74LVQ245 datasheet(1/8 Pages) STMICROELECTRONICS

No. de pieza	74LVQ245

Descripción Electrónicos	LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER 3-STATE

PDF	8 Pages

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

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74LVQ245

LOW VOLTAGE CMOS OCTAL BUS

TRANSCEIVER (3-STATE)

®

March 1999

ORDER CODES :

74LVQ245M

74LVQ245T

M

(Micro Package)

s

HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V

s

COMPATIBLE WITH TTL OUTPUTS

s

LOW POWER DISSIPATION:

ICC =5

µA (MAX.) at TA =25 oC

s

LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V

s

75

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL = 12 mA (MIN)

s

PCI BUS LEVELS GUARANTEED AT 24mA

s

BALANCED PROPAGATION DELAYS:

tPLH

≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 3.6V (1.2VData Retention)

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 245

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The LVQ245 is a low voltage CMOS OCTAL BUS

TRANSCEIVER

(3-STATE)

fabricated

with

sub-micron silicon gate and double-layer metal

wiring C

2MOS technology. It is ideal for low

power and low noise 3.3V applications.

It has better speed performance at 3.3V than 5V

LSTTL family combined with the true CMOS low

power consumption.

T

(TSSOP Package)

This IC is intended for two-way asynchronous

communication between data buses; the direction

of data trasmission is determined by DIR input.

The enable input G can be used to disable the

device so that the buses are effectively isolated.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

IT IS PROHIBITED TO APPLY A SIGNAL TO A

TERMINAL WHEN IT IS IN OUTPUT MODE

AND WHEN A BUS TERMINAL IS FLOATING

(HIGH IMPEDANCE STATE) IT IS REQUESTED

TO FIX THE INPUT LEVEL BY MEANS OF

EXTERNAL

PULL

DOWN

OR

PULL

UP

RESISTOR.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

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74LVQ245 Datasheet(PDF) 1 Page - STMicroelectronics

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