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STM32H523VCY6 Datasheet(PDF) 54 Page - STMicroelectronics |
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STM32H523VCY6 Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 228 page  Functional overview STM32H523xx 54/228 DS14540 Rev 1 • Configurable behavior at slave underrun condition (support of cascaded circular buffers) • Wake-up from Stop capability • Optional status pin RDY signalizing the slave device ready to handle the data flow. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in Master or Slave mode, in full-duplex communication modes, and can be configured to operate with configurable resolution as input or output channel. I2S main features: • Full duplex communication • Simplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler • Data length may be 16, 24 or 32 bits • Channel length can be 16 or 32 in master, any value in slave • Programmable clock polarity • Error flags signaling for improved reliability: Underrun, Overrun and Frame Error • Embedded Rx and TxFIFOs • Supported I2S protocols: – I2S Philips standard – MSB-Justified standard (Left-Justified) – LSB-Justified standard (Right-Justified) – PCM standard (with short and long frame synchronization) • Data ordering programmable (LSb or MSb first) • DMA capability for transmission and reception • Master clock can be output to drive an external audio component. The ratio is fixed at 256 x FWS (where FWS is the audio sampling frequency) 3.37 Secure digital input/output and MultiMediaCards interface (SDMMC) The SD/SDIO, embedded MultiMediaCard (e•MMC™) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices. Table 10. SPI features SPI feature SPI1, SPI2, SPI3 (full feature set instances) Data size Configurable from 4 to 32-bit CRC computation CRC polynomial length configurable from 5 to 33-bit Size of FIFOs 16x 8-bit Number of transfered data Unlimited, expandable I2S feature Yes |
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