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74VHCT126AM Datasheet(PDF) 1 Page - STMicroelectronics |
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74VHCT126AM Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 8 page  74VHCT126A QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA March 2000 PIN CONNECTION AND IEC LOGIC SYMBOLS s HIGH SPEED: tPD = 5 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN), VIL = 0.8V (MAX) s POWER DOWN PROTECTION ON INPUTS & OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 126 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.8V (Max.) DESCRIPTION The 74VHCT126A is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. This device requires the 3-STATE control input G to be set low to place the output into the high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ® SOP TSSOP ORDER CODES PACKAGE T UBE T & R SOP 74VHCT126AM 74VHCT126AMTR TSSOP 74VHCT126ATTR 1/8 |
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