ADC12L034 datasheet(8/35 Pages) NSC

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AC Electrical Characteristics (Continued)

The following specifications apply for V

+ =V

A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver-

sion mode, t

r =tf = 3 ns, fCK =fSK = 5 MHz, RS =25

Ω, source impedance for V

REF+ and VREF−

≤ 25Ω, fully-differential input

with fixed 1.250V common-mode voltage, and 10(t

CK) acquisition time unless otherwise specified. Boldface limits apply for

A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits (Note 11)

Units (Limits)

HDO

DO Hold Time from Serial Data Clock

Falling Edge

L = 3k, CL = 100 pF

ns (max)

ns (min)

DDO

Delay from Serial Data Clock Falling

Edge to DO Data Valid

ns (max)

RDO

DO Rise Time, TRI-STATE to High DO

Rise Time, Low to High

L = 3k, CL = 100 pF

ns (max)

FDO

DO Fall Time, TRI-STATE to Low DO

Fall Time, High to Low

L = 3k, CL = 100 pF

ns (max)

Delay from CS Falling Edge to DOR

Falling Edge

ns (max)

Delay from Serial Data Clock Falling

Edge to DOR Rising Edge

ns (max)

Capacitance of Logic Inputs

OUT

Capacitance of Logic Outputs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+orVD+), the current at that pin should be limited to 20 mA.

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is PD =(TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,

TJ max = 150˚C.

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND

will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude

of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05

VDC to ensure accurate conversions.

01183006

Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V

pin.

Note 9: With the test condition for VREF (VREF+−VREF−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV.

Note 10: Typical figures are at TJ =TA = 25˚C and represent most likely parametric norm.

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).

Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions

between 1 to 0 and 0 to +1 (see Figure 4).

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.

Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.

ADC12L034 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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