SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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Symbol

Parameter

Conditions

Min

Max

Units

tWL

Reset Pulse Width

2.5

ns

TRST (L)

tREC

Recovery Time

2.0

ns

TCK from TRST

fMAX

Maximum Clock Frequency, TCK

25

MHz

APPLICATIONS/PROGRAMMERS REFERENCE

Table 2. REGISTER SUMMARY

Address

Type

Mnemonic

Register

Active Register Bits

Reset Value

00h

RW

START

Start Register

5

0000h

01h

RW

STATUS

Status Register

10

0000h

02h

RW

INTCTRL

Interrupt Control Register

8

0000h

03h

RW

INTSTAT

Interrupt Status Register

8

0000h

04h

RW

SETUPR

Setup Register

8

0043h

05h

RW

CLKDIV

Clock Divider Register

6

0000h

07h

RW

EXPR

TDI_SM LFSR Exponent Register

3

0000h

08h

RW

LSSEDR

TDI_SM LSB Seed Register

16

0000h

09h

RW

MSSEDR

TDI_SM MSB Seed Register

16

0000h

0Ah

RW

LSRESR

TDI_SM LSB Result Register

16

0000h

0Bh

RW

MSRESR

TDI_SM MSB Result Register

16

0000h

0Ch

RW

INDEXR

Index Register

16

0000h

11h

RW

VINDEXR

Vector Index Register

16

0000h

13h

RW

HTINDEXR

Header/Trailer Index Register

16

0000h

15h

RW

MINDEXR

Macro Index Register

16

0000h

17h

RW

SINDEXR

Sequencer Index Register

16

0000h

19h

RW

BSINDEXR

Bridge Support Register

16

0000h

Table 3. MEMORY/REGISTER ADDRESS MAP

A4

A3

A2

A1

A0

Function

Base Address

Long Word

Structure/Size

Index

0

0

0

0

0

Start

N/A

N/A

16-bit Register

0

0

0

0

1

Status

N/A

N/A

16-bit Register

0

0

0

1

0

Interrupt Control

N/A

N/A

16-bit Register

0

0

0

1

1

Interrupt Status

N/A

N/A

16-bit Register

0

0

1

0

0

Setup

N/A

N/A

16-bit Register

0

0

1

0

1

Clock Divider

N/A

N/A

16-bit Register

0

0

1

1

1

TDI_SM LFSR Exponent

N/A

N/A

16-bit Register

0

1

0

0

0

TDI_SM LFSR LSB Seed

N/A

N/A

16-bit Register (1)

0

1

0

0

1

TDI_SM LFSR MSB Seed

N/A

N/A

16-bit Register (1)

0

1

0

1

0

TDI_SM LFSR LSB Result

N/A

N/A

16-bit Register (1)

0

1

0

1

1

TDI_SM LFSR MSB Result

N/A

N/A

16-bit Register (1)

0

1

1

0

0

Index Register

N/A

N/A

16-bit Register (2)

0

1

1

0

1

TDO_SM

0

0 - 0x1BF

See (3)

0

1

1

1

0

TDI_SM

0 x 1C0

0 - 0x1BF

See (3)

(1)

The TDI_SM LFSR result and seed registers require two sequential reads/writes for each register pair.

(2)

The Index register is used to set the individual address pointers. Writing to the Index register will set each of the individual address

pointers (TDO_SM, TDI_SM, Expected, and Mask). The individual address pointers will automatically increment with each long word

read from TDI_SM or each long word written to the TDO_SM, Expected, or Mask memory spaces.

(3)

The actual address is calculated from the base address of the memory area plus the content of its address pointer.

8

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