Nexperia

PRMD3

50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)

PRMD3

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Product data sheet

15 June 2017

3 / 15

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor, for the PNP transistor with negative polarity

VCBO

collector-base voltage

open emitter

-

50

V

VCEO

collector-emitter voltage open base

-

50

V

VEBO

emitter-base voltage

open collector

-

10

V

positive

-

40

V

VI

input voltage

negative

-

-10

V

IO

output current

-

100

mA

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

325

mW

Per device

Ptot

total power dissipation

Tamb ≤ 25 °C

[1]

-

480

mW

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-55

150

°C

Tstg

storage temperature

-65

150

°C

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.

Tamb (°C)

-75

175

125

25

75

-25

aaa-024487

200

300

100

400

500

Ptot

(mW)

0

FR4 PCB, standard footprint

Fig. 1. Per device: Power derating curve