6.3.4 Digital Output

A differential input signal of 0V ideally produces a stream of ones and zeros that is high 50% of the time.

A differential input of 250mV produces a stream of ones and zeros that is high 89.06% of the time. With 16

bits of resolution, that percentage ideally corresponds to code 58368. A differential input of 250mV produces a

stream of ones and zeros that are high 10.94% of the time. With 16 bits of resolution, that percentage ideally

corresponds to code 7168. These input voltages are also the specified linear range of the AMC0106M25. If the

input voltage value exceeds this range, the output of the modulator shows increasing nonlinear behavior as the

quantization noise increases. The modulator output clips with a constant stream of zeros with an input ≤320mV

or with a constant stream of ones with an input ≥320mV. In this case, however, the AMC0106M25 generates a

single 1 or 0 every 128 clock cycles to indicate proper device function. A single 1 is generated if the input is at

negative full-scale and a 0 is generated if the input is at positive full-scale. See the Output Behavior in Case of a

Full-Scale Input section for more details. Figure 6-4 shows the input voltage versus the output modulator signal.

Modulator Output

+ FS (Analog Input)

– FS (Analog Input)

Analog Input

Figure 6-4. Modulator Output vs Analog Input

The density of ones in the output bitstream is calculated using Equation 1 for any input voltage (VIN = VINP –

VINN) value. Except for a full-scale input signal, as described in Output Behavior in Case of a Full-Scale Input

section.

ρ=VIN+VClipping

2×VClipping

(1)

6.3.4.1 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC0106M25, the device generates a single one or zero every 128

bits at DOUT. Figure 6-5 shows a timing diagram of this process. A single 1 or 0 is generated depending on

the actual polarity of the signal being sensed. A full-scale signal is defined when |VIN| ≥ |VClipping|. In this way,

differentiating between a missing AVDD and a full-scale input signal is possible on the system level.

DOUT

CLKIN

127 CLKIN cycles

127 CLKIN cycles

VIN

–320 mV

VIN ≥ 320 mV

DOUT

Figure 6-5. Full-Scale Output of the AMC0106M25

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