www.ti.com

ADS5510

SLAS499 – JANUARY 2007

PIN CONFIGURATION (continued)

PIN ASSIGNMENTS(1)

TERMINAL

NO. OF

NAME

NO.

PINS

I/O

DESCRIPTION

5, 7, 9, 15, 22,

AVDD

24, 26, 28, 33,

12

I

Analog power supply

34, 37, 39

6, 8, 12, 13,

14, 16, 18, 21,

AGND

14

I

Analog ground

23, 25, 27, 32,

36, 38

DRVDD

49, 58

2

I

Output driver power supply

1, 42, 48, 50,

DRGND

6

I

Output driver ground

57, 59

NC

44, 45, 46

2

—

Not connected

INP

19

1

I

Differential analog input (positive)

INM

20

1

I

Differential analog input (negative)

REFP

29

1

O

Reference voltage (positive); 0.1-µF capacitor in series with a 1-

Ω resistor to GND

REFM

30

1

O

Reference voltage (negative); 0.1-µF capacitor in series with a 1-

Ω resistor to GND

IREF

31

1

I

Current set; 56-k

Ω resistor to GND; do not connect capacitors

CM

17

1

O

Common-mode output voltage

RESET

35

1

I

Reset (active high), 200-k

Ω resistor to AV

DD

(2)

OE

41

1

I

Output enable (active high)

DFS

40

1

I

Data format and clock out polarity select(3)(4)

CLKP

10

1

I

Data converter differential input clock (positive)

CLKM

11

1

I

Data converter differential input clock (negative)

SEN

4

1

I

Serial interface chip select(4)

SDATA

3

1

I

Serial interface data(4)

SCLK

2

1

I

Serial interface clock(4)

D0 (LSB) to

47, 51-56,

11

O

11 bit parallel data output

D10 (MSB)

60-63

OVR

64

1

O

Over-range indicator bit

CLKOUT

43

1

O

CMOS clock out in sync with data

(1)

PowerPAD is connected to analog ground.

(2)

If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.

(3)

Table 3 defines the voltage levels for each mode selectable via the DFS pin.

(4)

Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins

must also run off the same supply voltage as DRVDD.

11

Submit Documentation Feedback