L9945 datasheet(19/144 Pages) STMICROELECTRONICS

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Functional description

This section contains the functional description of this device. A general description of the device functionality is

provided along with the detailed operation of each sub-block. Relations and interconnections between various

sub-blocks are explained. For a detailed diagnostic analysis, refer to Section 6.2: Diagnostics overview.

5.1

General description

The device contains eight pre-drivers for external FETs. Each pre-driver can be configured to drive a high-side or

low-side external driver (LS_HS_config_xx bit). The external FET can be either N-channel (low-side and high-

side) or P-channel (high-side). FET type is selectable through N_P_config_xx bit. Complex configurations for

P&H and H-Bridge are automatically applied programming the corresponding bit via SPI (HBx_config or

PHx_config).

The outputs are controlled either directly by pins NONx or via SPI commands (programming SPI_ON_OUTxx bit).

For each channel, control strategy is selected by programming the SPI_input_sel_xx bit.

Output channels must be enabled prior to use by programming the en_OUT_xx bit in the corresponding output

load control).

IC provides charge pump for driving external low-side and high-side NMOS. Gate charge/discharge currents can

be either constant, with value selectable via SPI, or limited by external resistor. GCC_config_xx bit defines the

charge/discharge strategy. An external capacitor connected between transistor gate and drain is recommended to

improve EMI performances.

External FET is protected against overcurrent (OC) during the ON phase by rapidly switching OFF the transistor

with a high gate current in case of OC detection. The value of such shutdown current can be programmed via the

GCC_OVERRIDE_CONFIG bit. Two detection strategies are available: either monitoring the voltage between

transistor drain and source (DSM) or monitoring the drop on an external shunt resistor. Detection strategy is

selectable via OC_DS_Shunt_xx bit. OC threshold is programmable via SPI (OC_config_xx bit). The device

offers the possibility of compensating the OC threshold with respect to temperature (OC_Temp_comp_xx bit) and

battery variations (OC_Batt_comp_xx bit). In case of an OC event, output re-engagement strategy is selectable

through prot_config_xx bit.

Detection of Open Load (OL) and STB/STG failures is performed during the OFF phase. The diagnostic phase

durations and currents can be selected through tdiag_config_xx and diag_i_config_xx bit.

In peak and hold configuration, the OFF diagnostic strategy can be programmed through PHx_diag_strategy bit.

In H-Bridge mode, the dead time to avoid cross conduction on the same branch of the bridge can be programmed

through the HBx_dead_time bit. An extended set of OFF diagnostic times is available for the H-Bridge mode by

programming the HBx_tdiag_ext_config bit.

A current limitation feature is available for H-Bridge configuration.

The diagnostic status of each channel is reported in the next received frame after having sent the following SPI

command: 0x9AAA0001.

Note:

The "x" in the bit names symbolize the generic channel number or the configuration index (e.g. NONx refers to

NON1, NON2, … , NON8. PHx_diag_strategy refers to PH1_diag_strategy and PH2_diag_strategy).

5.2

Supply concept

The device has 4 supply pins: VDD5, VPS, VGBHI, and VIO.

•

VDD5 has to be provided by the ECU power supply and feeds most of the internal sub-blocks. Two internal

regulators are used to generate separate 3.3 V supplies for analog and digital domains.

•

VPS has to be provided by the battery and is used to feed the internal charge pump.

•

VGBHI is the output voltage of the charge pump and it is used for driving the gate of the external FETs.

•

VIO is a separate power supply dedicated for the SDO pin of the Serial Peripheral Interface. It must be

connected to the same voltage level of the SPI master. The VIO pin is implemented in order to be

compliant with both 3.3 V and 5 V systems.

5.2.1

VDD5 supply block

The VDD5 pin is internally split between analog and digital domain to reduce interference between the different

parts of the component. Two regulators are implemented in order to provide separate 3.3 V domains:

L9945

Functional description

DS12275 - Rev 10

page 19/144

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