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FC106 Datasheet(PDF) 8 Page - STMicroelectronics

No. de pieza FC106
Descripción Electrónicos  Fibre Channel Transceiver 1.0625 GBaud
PDF  32 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

FC106 Datasheet(HTML) 8 Page - STMicroelectronics

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FC106
Revision 1.2
8/32
September 98
3.1
Block diagram
Figure 3.1
Block diagram
3.2
Input latches
The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0:9]. The user-provided
reference clock signal REFCLK is also used as the transmit byte clock. The TX[0:9] and
REFCLK signals must be properly aligned, as shown in Section 6.1:
Transmit interface
timing and latency on page 20.
RCB[0:1]
REFCLK
XOR
Tree
JTAG
CONTROL
transmitter
TX+
TX-
RS (*)
AT (*)
TX [0:9]
8b/10b
decoder
DLL clock generator
Clock Recovery
ZC
setting
ENC
DESERIALIZER
SERIALIZER
ENC
TCK(*)
TRSTN(*)
TMS(*)
TDI(*)
TDO(*)
TEST ENABLE(*)
rece iver
ZC+(*)
ZC-(*)
RX-
RX+
8b/10b
encoder
Word
Align-
ment
Bit
Align-
ment
SELF
TEST
(*)Test signals not
included in FCS
10-bit interface
EWRAP
COM_DET
EN_CDET
RX[0:9]



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