5.3

Application design tips

In Figure 6 below a typical application schematics is shown:

Figure 6. Typical application schematics

VDD

VDDIS O

VIN-

VIN+

N

L

VDDISO

VDD

M

330n

10R

1

2

3

4

5

6

7

8

9

10

11

12

13

15

14

16

10u

MCKIN- (LVDS only)

1

10u

MDAT- (LVDS only)

1

330n

100n

100n

10R

VDD

1

2

Shunt

MCKIN+/MCKIN

1

VDDISO

1

2

MDAT+/MDAT

1

Large use of capacitors on both VDDiso and VDD supply pins for decoupling is strongly recommended.

Though the device can withstand high transients across the isolation barrier, the application designer must take

care of board coupling between the analog front-end and the digital back-end domains. They must also take

design actions in order to avoid any loss of clearance and creepage distances. Failure to ensure these can lead to

severe permanent damage.

The analog input tracks should be kept symmetrical and equalized in impedance, to minimize additional offset.

The use of ground planes for noise reduction is recommended.

For LVDS digital interfacing, the use of termination resistors (typically 100 ohm) is recommended.

ISOSD61

Theory of operation

DS13605 - Rev 11

page 14/23