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ICS87421AMIFT Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS87421AMIFT Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 14 page ![]() IDT™ / ICS™ LVDS CLOCK GENERATOR 8 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V R1 50 R3 50 Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input R2 50 Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V R3 125 R2 84 Zo = 50 Ohm 3.3V R4 125 LVPECL R1 84 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the V PP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V R2 50 Input LVHSTL Driver ICS HiPerClockS R1 50 LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER Zo = 50 Ohm R1 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiv er CLK nCLK 3.3V HCSL *R3 33 *R4 33 CLK nCLK 2.5V 3.3V Zo = 50 Ω Zo = 50 Ω HiPerClockS Input R1 50 R2 50 *Optional – R3 and R4 can be 0 Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER CLK nCLK HiPerClockS SSTL 2.5V Zo = 60 Ω Zo = 60 Ω 2.5V 3.3V R1 120 R2 120 R3 120 R4 120 |
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