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XIO2001IPNP Datasheet(PDF) 82 Page - Texas Instruments |
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XIO2001IPNP Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 145 page  8.4.69 Clock Run Status Register The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 8-52 for a complete description of the register contents. PCI register offset: DAh Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 8-52. Clock Run Status Register Description BIT FIELD NAME ACCESS DESCRIPTION 7:1 RSVD R Reserved. Returns 000 0000b when read. 0(1) SEC_CLK_STATUS RU Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs. 0 = Secondary clock running 1 = Secondary clock stopped (1) These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 www.ti.com 82 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: XIO2001 |
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