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RF2705G
Rev A0 DS060206
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Application Information
The baseband inputs of the RF2705 must be driven with balanced signals. Amplitude and phase matching <0.5dB and <0.5
degrees are recommended. Phase or gain imbalances between the complementary input signals will cause additional distor-
tion including some second order baseband distortion.
The RF2705 is designed to be driven with either single-ended or differential LO signals. Driving the chip differentially is benefi-
cial in improving the LO leakage performance. Decreasing the LO drive level will also improve LO leakage, but the output noise
performance will be degraded. Driving the LO level too high will degrade linearity.
The ground lines for the LO sections are brought out of the chip independently from the ground to the RF and modulator sec-
tions. This is intended to give the board design the independence of isolating the LO signals from the RF output sections.
The RF2705 includes frequency doubler and divider modes that allow the LO to operate at half or twice the frequency depend-
ing on the application. This provides some flexibility in improving VCO isolation and LO leakage through frequency translation.
The RF outputs use open collector architecture and may be biased at voltages higher than VCC. In practice, biasing at a higher
voltage may improve the intermodulation performance. The load resistors are selected to provide sufficient output power while
maintaining good linearity.
The GC DEC and VREF output pins should be decoupled to ground. A 10nF capacitor on VREF and a 1nF capacitor on GC CEC
are recommended. The purpose of these capacitors is to filter out low frequency noise (20MHz) in the gain control lines that
may cause noise on the RF signal. The capacitor on the GC DEC line will effect the settling time of the step response in power
control voltage. A 1nF capacitor equates to around a 200ns settling time; a 0.5nF capacitor equates to a 100ns settling time.
There is a trade-off between setting time and phase noise as gain control is applied.
As with any RF circuit, the RF2705 is sensitive to PC board layout. The suggested schematic and board layout is included as a
guideline. Proper grounding of the die flag under the chip is essential in achieving acceptable RF performance. A symmetric
output structure will maintain signal balance while keeping the RF lines short will reduce losses. Proper routing and bypassing
of the supply lines will improve stability and performance, especially under low gain control settings where carrier suppression
becomes crucial. The location and value of the bypass capacitor on pin 1 is critical in promoting good carrier suppression and
is designated to resonate out the series wire bond and PC board inductance.
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