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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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CY28323PVC Datasheet(PDF) 17 Page - SpectraLinear Inc |
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CY28323PVC Datasheet(HTML) 17 Page - SpectraLinear Inc |
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17 / 21 page  CY28323PVC Rev 1.0, November 24, 2006 Page 17 of 21 - Switching Characteristics[[3]] Over the Operating Range Parameter Output Description Test Conditions Min. Max. Unit t1 All Output Duty Cycle[[4]] t1A/(t1B) 45 55 % t2 CPU Rise Time Measured at 20% to 80% of Voh 175 700 ps t2 48MHz, REF Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t2 PCI, 3V66, Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU Fall Time Measured at 80% to 20% of Voh 175 700 ps t3 48MHz, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 V/ns t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t5 3V66 [0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66,PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V 1.5 3.5 ns t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 200 ps t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 48MHz Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps CPU, PCI Settle Time CPU and PCI clock stabilization from power-up 3 ms CPU Rise/Fall Matching Measured with test loads[[5], [6]] 20% CPU Overshoot Measured with test loads[[6]] Voh + 0.2 V CPU Undershoot Measured with test loads[[6]] –0.2 V Voh CPU High-level Output Voltage Measured with test loads[[6]] 0.65 0.74 V Vol CPU Low-level Output Voltage Measured with test loads[[6]] 0.0 0.05 V Vcrossover CPU Crossover Voltage Measured with test loads[[6]] 45% of 0.65 55% of 0.74 V Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 5. Determined as a fraction of 2*(tRP – tRN)/(tRP +tRN) Where tRP is a rising edge and tRN is an intersecting falling edge. 6. The test load is Rs = 33.2 , Rp = 49.9 in test circuit. |
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