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ST7FLCD1 Datasheet(PDF) 23 Page - STMicroelectronics

No. de pieza ST7FLCD1
Descripción Electrónicos  8-bit MCU for LCD Monitors with 60 KBytes Flash,2 KBytes RAM, 2 DDC Ports and Infrared Controller
PDF  95 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7FLCD1 Datasheet(HTML) 23 Page - STMicroelectronics

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ST7FLCD1
Reset
3.2
Watchdog or Illegal Opcode Access Reset
For more information about the Watchdog, please refer to Section 12: Watchdog Timer (WDG)
An Illegal Opcode reset occurs if the MCU attempts to execute a code that does not match a valid
ST7 instruction.
3.3
External Reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 9, the RESET signal must remain low for a minimum of 1 µs.
An internal Schmitt trigger and filter provided at the RESET pin improve noise immunity.
3.4
Reset Procedure
At power-up, the MCU follows the sequence described in Figure 9.
Note:
Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM.
Figure 8: Reset Generation Diagram
Figure 9: Reset Timing Diagram
Low Voltage Detector
RESLVD
VDD
RESET
Watchdog
Illegal Opcode Access
External Reset
Reset
VDD
OSCIN
fCPU
FFFF
FFFE
PC
RESET
Watchdog Reset
tDDR
tOXOV
4096 CPU
Clock Cycle
Delay



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