MPC8245 datasheet(8/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 2 shows supply voltage sequencing and separation cautions.

Figure 2. Supply Voltage Sequencing and Separation Cautions

OVDD/GVDD/(LVDD @ 3.3 V - - - -)

VDD/AVDD/AVDD2

LVDD @ 5 V

Time

3.3 V

5 V

2.0 V

7, 9

Reset

Configuration Pins

HRST_CPU,

HRST_CTRL

PLL

Relock

Time 3

100 µs

Nine External Memory

Asserted 255

External Memory

HRST_CPU,

HRST_CTRL

VDD Stable

Power Supply Ramp Up 2

See Note 1

Clock Cycles 3

Clock Cycles Setup Time 4

VM = 1.4 V

Maximum Rise Time Must Be Less Than

One External Memory Clock Cycle 5

Notes:

1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.

2. See the Cautions section of Table 2 for details on this topic.

3. See Table 8 for details on PLL relock and reset signal assertion timing requirements.

4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements.

5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one

SDRAM_SYNC_IN clock cycle for the device to be in the nonreset state.

6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the

negation of HRST_CTRL and HRST_CPU in order to be latched.

PLL

MPC8245 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc

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