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TDA7500A Datasheet(PDF) 21 Page - STMicroelectronics |
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TDA7500A Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 40 page ![]() 21/40 TDA7500A SPI INTERFACES Figure 6. SPI Clocking scheme. 10 WORDS MAIN MICRO SPI Symbol Description Min Value Unit MASTER tsclk Clock Cycle 12TDSP ns tdtr Sclk edge to MOSI valid 40 ns tmisosetup MISO setup time 16 ns tmisohold MISO hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns SLAVE tsclk Clock Cycle 12TDSP ns tdtr Sclk edge to MOSI valid 40 ns tmosisetup MOSI setup time 16 ns tmosihold MOSI hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns DISPLAY SPI (different timings) MASTER tsclk Clock Cycle 6TDSP ns SLAVE tsclk Clock Cycle 6TDSP ns SCLKD, SCLKM (#6, #10) (CPOL=0, CPHA=0) MISOM, MOSIM (#7, #8) MISOD, MOSID (#11, #12) SSM, SSD (#9, #13) (CPOL=0, CPHA=1) (CPOL=1, CPHA=0) (CPOL=1, CPHA=1) Internal Strobe for Data Capture MSB 6 5 4 3 2 1 LSB SCLKD, SCLKM (#6, #10) SCLKD, SCLKM (#6, #10) SCLKD, SCLKM (#6, #10) |
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